The present invention relates to a read only memory (ROM) semiconductor device of the type in which a contact method is employed for data writing.
In the ROM semiconductor device, to write data, a mask is used during the process of manufacturing the wafer. In this sense, the ROM of this type is called a mask programmable ROM. There have been known several methods to write data into the ROM. One of the data writing methods is a contact method in which data lines selectively contact with specific portions of the semiconductor structure, for example, drain regions of memory cell transistors. Another method is a field oxide programming method in which a transistor or transistors are selectively completed for data writing. A further method is to set the threshold voltage of memory cell transistors at a proper value for data writing.
From a structural viewpoint of the memory cell, the ROM is categorized into a NOR ROM and an NAND-NOR ROM. From an operational viewpoint, the ROM is categorized into a synchronous ROM and an asynchronous ROM. For a high operating speed application, the NOR ROM is employed, while for a low operating speed
The data writing method most popularly employed, for the NOR ROM, suitable for a high operating speed application, is the contact method. The contact method is easy and reliable in writing data. In the contact method, the writing process is in the latter half step of the overall ROM manufacturing process and the turnaround time is short.
An example of the prior art ROM pattern based on the contact method is illustrated in FIG. 1 as viewed from the top. In the memory device, memory cells, one of which is typically enclosed by a broken line in FIG. 1, are arrayed in a matrix fashion. Each memory cell is made of a single MOS transistor. The memory cell 1 is structurally composed of a single crystal silicon region 2 doped with an impurity serving as the drain of each of MOS transistors, a diffusion region 3, word lines 4 made of polysilicon, and data lines 6. The diffusion region 3 serves as the source common to the MOS transistors in a row direction of the matrix array. Each word line 4 extends horizontally and forms the gate electrode common to those MOS transistors arranged in a row direction. The data lines 6 are vertically arranged and are selectively connected to the drains of the MOS transistors through contact holes 5.
The ROM thus structured may electrically be expressed as shown in FIG. 2. In the ROM, the connection or nonconnection of the drains of the MOS transistors through the contact holes to the data lines 6 respectively provide logical "1" or "0".
The ROM with the pattern as shown in FIG. 1 has the physical contacts of the silicon region 2 with the data lines 6 via the contact holes 5. The data line 6 is made of aluminum. For securing a good contact, a minimum contact resistance is required at the interface between the data line 6 and the silicon region 2. By the way, the work function of silicon is different from that of aluminum. Contact resistance when materials with different large. A simple and effective measure to reduce, contact resistance between the region 2 and the data line 6 is to enlarge an area of the contact holes 5 and a contact area between the region 2 with the data line 6. Further, to prevent an erroneous contact between the data line 6 and the semiconductor substrate, it is required that the diffusion region 2 is much larger than the size of the contact holes 5. Therefore, an area occupied by each memory cell is large, imparing an integration density. These facts become problematic particularly in large capacity ROMs.